Hardware Architecture Proposal for TEDA Algorithm to Data Streaming Anomaly Detection

The amount of data in real-time, such as time series and streaming data, available today continues to grow. Being able analyze this the moment it arrives can bring an immense added value. However, also requires a lot computational effort new acceleration techniques. As possible solution problem, paper proposes hardware architecture for Typicality Eccentricity Data Analytic (TEDA) algorithm implemented on Field Programmable Gate Arrays (FPGA) use anomaly detection. TEDA is based approach outlier detection stream context. suggested design has full parallel input N elements 3-stage pipelined reduce critical path thus optimize throughput. In order validate proposals, results occupation throughput proposed are presented. reached speed up 693x, compared other software platforms, with 10.96 MSPs (Mega Sample Per second), using small portion target FPGA resources. Besides, bit accurate simulation This work pioneer implementation technique FPGA. project aims Xilinx Virtex-6 xc6vlx240t-1ff1156